A FIFO buffer with non-blocking interface

The design of a FIFO buffer supporting synchronisation-free, non-blocking, reading and writing operations is presented. The circuit consists of a standard self-timed FIFO surrounded by two interface blocks, In and Out, which together provide temporal independence between the reader and writer processes. These blocks are synthesised from their Signal Transition Graph (STG) specifications using an asynchronous circuit synthesis tool, Petrify. The proposed solution is compared with “slot” mechanisms. It is shown to be more appropriate for “profile data” applications, such as video or audio transmissions. Introduction Real time systems often need to provide data communication between subsystems with independent timing of the send and receive procedures. Similar problems arise in modern VLSI chips where new forms of asynchronous communication between modules need to be found to sustain various technological advances, such as the ability to accommodate subsystems with different clocks on the same chip. For such applications, any scheme involving any temporal blocking between a pair of Reader and Writer processes may not be acceptable. Here it is assumed that shared memory is used between Reader and Writer, in the form of Fig 1 in [1]. For finite systems of this type, two necessary consequences of providing temporal independence for Reader and Writer (or completely “de-coupling” them temporally) are data loss and rereading of old data. In other words, Writer must be allowed to skip or overwrite data which has not been read by Reader, and Reader must be allowed to re-read old data it has already obtained in a previous cycle of operation. Such asynchronous communication mechanisms (ACMs), however, should possess such properties as data coherence and data freshness. The former implies that Reader should not access data that is being written and Writer should not attempt writing to data that is being read. The latter implies that Reader should ideally be able to obtain the newest possible data item available, given the physical limitations of the device being designed. Another important property of ACMs is data sequencing, which implies that Reader should ideally at no time obtain an item of data older than the item obtained during its previous cycle. Most of the ACMs published to date involve multiple data slots, which are organised in a conceptually parallel/transverse fashion. This implies that each data slot may be potentially accessible to either Reader or Writer at any time. Potential conflicts on any single slot are normally resolved by the use of control variables. Examples of these types of mechanisms can be found in [2]. They are referred to as slot mechanisms here. The slot mechanisms, because of the transverse organisation of slots, do not provide the design flexibility to influence the data loss, re-reading, and sequencing properties of implementations. The designers are left claiming that data loss and data re-reading are “inevitable consequences of synchronisation-free data communication” and leaving data sequencing to fortune. As a result, certain designs are able to maintain data sequencing but others, obtained using similar methods, not. To date there is no clear idea as to why this is the case [3]. This has resulted in the designers’ targeting “reference data” type applications for the slot mechanisms. In order to broaden the application field of non-blocking ACMs, a design is presented here which provides some means of adjusting the data loss and re-reading rates while providing data coherence and sequencing. Data freshness requirements have been relaxed to allow a measure of latency into the ACM, which would be more suitable for “profile data” applications such as speech and image data. This type of data is more context sensitive than “reference data”. On the other hand, absolute minimum latency is not always required in transmission. FIFO buffer design The classical bounded self-timed buffer [4] helps to smooth out any temporary differences in the rate between data writing and reading. However, if the average speeds of Reader and Writer differ it would eventually start blocking (obliging waiting) the activity of the faster party. A FIFO buffer has been designed with non-blocking Writer and Reader interfaces. In this design, if Writer attempts to write when the buffer is full, the data will be “skipped”. The skipped data, if tagged appropriately, may in principle be collected for future use but such functionality is outside the scope of this circuit. Similarly, if the buffer is empty while Reader attempts to read, the buffer will send a special acknowledgement so that Reader may use the previously read data item. These are the data loss and re-reading provisions to ensure nonblocking. The structure of the buffer is shown in Figure 1. It has a fairly standard handshake interface with Writer and Reader via the In and Out blocks. The use of handshakes in In and Out is purely for convenience and does not imply any blocking synchronisation, as the following conditions for the In block show (similar conditions apply for the Out block). Writer Reader WrReq WrAck Real-Time FIFO WrData RdData RdReq RdAck RdOld Self-Timed FIFO OutData OutReq OutAck WrData WrReq WrAck In SkpData SkpReq RdData RdReq